Techoverse

本文移植於tutortecho 2020年9月19日 撰寫

Q1:At a test plan level, how would you verify a 4 port switch? It has 4 symmetric, bidirectional ports, all of which send and receive packets having the following fields: source, destination, data length, data, parity check.

2: Design a driver to fit this behavior

Ans: (Not support back to back)

task run_phase(uvm_phase phase) begin

 forever begin

  while(!(vif.req & vif.gnt)) begin

   @(posedge clk);

end

  tr.wr = vif.we;

  if(vif.we == 1’b0) begin

   while(vif.rsp != 1’b1) begin

    @(posedge clk);

end

tr.data = data1;

end else begin

   tr.data = data0;

  end

  port.write(tr);

  @(posedge clk);

 end



end